A liquid crystal panel has an advantage in that it is thin and light, and consumes less electric power. Therefore, liquid crystal panels are used widely in, for example, portable terminal devices such as mobile telephones and PDAs, and electronic equipment such as personal computers, television sets, video cameras, and digital cameras.
FIG. 4 shows an example of a Chip On Glass (COG) type liquid crystal panel 100 that has been used conventionally. The liquid crystal panel 100 includes an active matrix substrate 101, and a counter substrate 102 opposed to the active matrix substrate 101. A liquid crystal layer (not shown) is interposed between the active matrix substrate 101 and the counter substrate 102.
The active matrix substrate 101 has a display area 103, a lead-out line area 104, and a mounting area 105. The display area 103 is an area in which gate lines 103a and source lines 103b are formed so as to cross each other orthogonally. Through the lead-out line area 104, the gate lines 103a and the source lines 103b are led out. The mounting area 105 is intended to mount, for example, a driving circuit (not shown). It should be noted that one edge of the liquid crystal panel 100 is referred to as a first edge 100a (the lower edge in FIG. 4), the edges thereof on the left and right sides with respect to the first edge 100a are referred to as a second edge 100b and a third edge 100c, respectively, and the edge thereof opposed to the first edge 100a is referred to as a fourth edge 100d. 
In the mounting area 105, a plurality of gate terminals 105a and a plurality of source terminals 105b are formed. The plurality of gate terminals 105a and the plurality of source terminals 105b are formed in one area of the active matrix substrate 101 so as to narrow a frame part of the liquid crystal panel 100 (see JP 2003-241217 A, for example).
When the active matrix substrate 101 and the counter substrate 102 are aligned to each other, the mounting area 105 of the active matrix substrate 101 is positioned closer to the first edge 100a as compared with the counter substrate 102. Therefore, the second edge 100b of the active matrix substrate 101 has a length H longer than a length L of the second edge 100b of the counter substrate 102.
In the display area 103, the plurality of gate lines 103a1, 103a2, . . . 103am are formed in a row direction (left-right direction in FIG. 4), and the plurality of source lines 103b1, 103b2, . . . 103bn are formed in a column direction (top-bottom direction in FIG. 4). Thin-film transistors (TFT) (not shown), and pixel electrodes (not shown) connected with the thin film transistors are formed at intersection portions between the gate lines 103a and the source lines 103b. 
Upper gate lead-out lines 106 are connected with the gate lines 103 formed in an upper side (the fourth edge 100d side) part of the display area 103, as well as to the gate terminals 105a formed in the mounting area 105. The upper gate lead-out lines 106 are formed along the third edge 100c. Lower gate lead-out lines 107 are connected with the gate lines 103a formed in a lower side (the first edge 100a side) part of the display area 103, as well as to the gate terminals 105a formed in the mounting area 105. The lower gate lines 103a are formed along the second edge 100b. It should be noted that FIG. 5 shows a modification example of the liquid crystal panel 100 shown in FIG. 4, in which the plurality of gate lines 103a1, 103a2, . . . 103am are lead out alternately to the second edge 100b side and to the third edge 100c side.
A line-break-inspection line 108 for the upper gate lines is connected with respective extension lines extended individually from the plurality of gate terminals 105a to which the upper gate lead-out lines 106 are connected. The line-break-inspection line 108 for the upper gate lines also are connected with an upper gate line inspection pad 109. Since the line-break inspection line 108 for the upper gate lines is connected with the upper gate line inspection pad 109, it is possible to feed a gate inspection signal from the upper gate line inspection pad 109 to the upper gate lines 103a via the upper gate lead-out lines 106 at once.
A line-break-inspection line 110 for the lower gate lines is connected with respective extension lines extended individually from the gate terminals 105a connected with the lower gate lead-out lines 107. Further, the line-break-inspection line 110 for the lower gate lines are connected with a lower gate line inspection pad 111. Since the line-break-inspection line 110 for the lower gate lines is connected with the lower gate line inspection pad 111, it is possible to feed a gate inspection signal from the lower gate line inspection pad 111 to the lower gate lines 103a via the lower gate lead-out lines 107 at once.
Source lead-out lines 112 are connected with the source lines 103b formed in the display area 103, and with the source terminals 105 formed in the mounting area 105. Source-side switching elements 113 are connected with the source lines 103b. Source lead inspection lines 114 are connected with the source-side switching elements 113 and source line inspection pads 115. The source lead inspection lines 114 are formed along the third edge 100c and the fourth edge 100d. 
The source line inspection pads 115 includes a switching pad 115a fed with a control signal for turning on/off of the source-side switching elements 113, an inspection pad 115b fed with a source inspection signal to be fed to the odd-numbered source lines 103b1, 103b3, . . . 103bn-1, and an inspection pad 115c fed with a source inspection signal to be fed to the even-numbered source lines 103b2, 103b4, . . . 103bn. This configuration allows different source inspection signals to be fed to adjacent source lines (for example, the source line 103b1 and the source line 103b2), respectively.
A common inspection line 116 positioned on the second edge 100b side part of the lead-out line area 104 is connected with a common electrode pad 117. Further, the common inspection line 116 also is connected with a common line 118 formed so as to surround the display area 103. The common line 118 has transfer pads 118a, The transfer pads 118a are connected with a common electrode (not shown) formed on the counter substrate 102. This allows a common voltage to be applied from the common electrode pad 117 to the common electrode formed on the counter substrate 102.
In the liquid crystal panel 100 as described above, an electrical connection state of the active matrix substrate 101 is inspected before a driving circuit is mounted on the mounting area 105 (see JP 2004-325956 A and JP 2005-241988 A, for example). As a method for inspection, the following method is used: probes for inspection (not shown), for example, are brought into contact with the upper gate line inspection pad 109, the lower gate line inspection pad 111, the source line inspection pads 115, and the common electrode pad 117, so that a gate inspection signal is fed to the gate lines 103a while a source inspection signal is fed to the source lines 103b. With this, the orientation directions of liquid crystal molecules are controlled, and, for example, when the liquid crystal panel 100 is irradiated from the back side with an illumination means such as a backlight, the display area 103 of the liquid crystal panel 100 displays an image. Therefore, an electrical connection state of the active matrix substrate 101 can be inspected by, for example, an inspector's visual observation, on the display area 103 of the liquid crystal panel 100.
For example, a gate inspection signal is fed from the upper gate line inspection pad 109 to the upper gate lines 103a and the upper gate lead-out lines 106. A gate inspection signal is fed from the lower gate line inspection pad 111 to the lower gate lines 103a and the lower gate lead-out lines 107. This allows any break in the gate lines 103a and the gate lead-out lines 106 and 107 to be detected on the display area 103 of the liquid crystal panel 100.
Further, the source inspection signals are fed from the source line inspection pads 115 to the source lines 103b and the source lead-out lines 112. This allows any break in the source lines 103b to be detected on the display area 103 of the liquid crystal panel 100. Further, to adjacent ones of the source lines 103b, different source inspection signals are fed from the source line inspection pads 115. This allows any short circuit (leak) of the source lines 103b and the source lead-out lines 112 to be detected on the display area 103 of the liquid crystal panel 100.